Memory Glossary

AMD's equivalent of Intel XMP, providing pre-configured overclocking profiles optimized for AMD Ryzen platforms. EXPO profiles are stored in the module's SPD alongside any XMP profiles.

The maximum theoretical data transfer rate of a memory module or channel, measured in MB/s or GB/s. Calculated as: Data Rate (MT/s) × Bus Width (bytes) = Bandwidth (MB/s).

For a single DDR5-4800 module: 4800 × 8 = 38,400 MB/s (38.4 GB/s). In a dual-channel configuration, this doubles to 76.8 GB/s. Actual throughput is typically lower due to protocol overhead, refresh cycles, and access patterns.

An independent array of memory cells within a DRAM chip where data is temporarily stored. When the memory controller accesses a bank, it activates a row and reads or writes columns within that row.

DDR3 chips have 8 banks, DDR4 has 16 banks (organized in 4 bank groups), and DDR5 has 32 banks (organized in 8 bank groups). Having more banks allows more concurrent operations and improves overall throughput.

A grouping of banks within a DRAM chip that allows faster back-to-back accesses when alternating between different groups. Introduced with DDR4 to improve bandwidth efficiency.

DDR4 x4/x8 devices have 4 bank groups of 4 banks each; x16 devices have 2 bank groups of 4 banks. DDR5 doubled this to 8 bank groups of 4 banks for x4/x8 devices. Accessing different bank groups has a shorter timing penalty (tCCD_S) than accessing within the same bank group (tCCD_L).

The number of data words transferred in a single read or write operation. DDR3 and DDR4 use a burst length of 8 (BL8), while DDR5 supports burst lengths of 8 and 16 (BL16).

A longer burst length means more data is transferred per command, improving bandwidth efficiency. DDR5's BL16 combined with its 32-bit sub-channels transfers 64 bytes per burst (matching a typical CPU cache line), compared to DDR4's 64 bytes from BL8 on a 64-bit bus.

A JEDEC-standardized memory module form factor that uses a compression connector instead of an edge connector. Originally developed by Dell, CAMM2 enables thinner laptop designs while supporting high memory capacities up to 128 GB.

Unlike SODIMMs that plug into a socket via edge pins, CAMM2 modules press flat against the motherboard using a compression connector and are secured with screws. JEDEC supports DDR5 CAMM2 and LPDDR5 CAMM2 variants, which are not interchangeable.

The total amount of data a memory module can store, expressed in gigabytes (GB). Module capacity is determined by the DRAM density, chip organization, and number of ranks.

For a kit (multiple modules sold together), the listed capacity is the combined total. Common capacities are 8 GB, 16 GB, and 32 GB for consumer modules, and 32 GB, 64 GB, 128 GB, or 256 GB for server RDIMMs and LRDIMMs.

The number of clock cycles between the memory controller sending a read command (column address) and the data being available on the output pins. CAS Latency is the most commonly cited memory timing parameter.

Lower CL values mean faster access, but CL must be evaluated together with the clock speed. For example, DDR4-3200 CL16 and DDR5-4800 CL40 have similar real-world latency in nanoseconds because DDR5 runs at a higher clock frequency. The formula is: Latency (ns) = CL / (Data Rate / 2) × 1000.

The data width of an individual DRAM chip, expressed as x4, x8, or x16. This determines how many data bits each chip contributes per access and affects which module types the chip can be used in.

x4 chips output 4 bits per access and are used in RDIMMs and LRDIMMs for servers (they enable advanced ECC with chipkill/SDDC). x8 chips output 8 bits and are used across all module types. x16 chips output 16 bits and are limited to UDIMMs and SODIMMs for desktops and laptops. The choice of DRAM width affects the number of chips needed per rank and the ECC capabilities.

A DDR5 SODIMM with a Client Clock Driver (CKD) for improved signal integrity at speeds of 6400 MT/s and above. The laptop equivalent of CUDIMM.

A DDR5 UDIMM that includes a Client Clock Driver (CKD) component to buffer the clock signal between the memory controller and DRAM chips. Required by JEDEC for DDR5 speeds of 6400 MT/s and above.

The CKD improves signal integrity and stability at higher data rates by regenerating the clock signal on the module. This allows unbuffered modules to achieve speeds that would otherwise be unreliable without clock buffering. CUDIMMs are backward compatible with standard DDR5 UDIMM sockets.

The speed at which data is transferred to and from a memory module, measured in megatransfers per second (MT/s). Because DDR memory transfers data on both clock edges, the data rate is twice the actual clock frequency.

For example, DDR5-4800 operates at a 2400 MHz clock frequency but achieves 4800 MT/s because data is transferred on both the rising and falling edges. The effective bandwidth of a module can be calculated by multiplying the data rate by 8 (bytes per transfer): DDR5-4800 provides 38,400 MB/s (38.4 GB/s) per module.

A type of synchronous DRAM that transfers data on both the rising and falling edges of the clock signal, effectively doubling the data rate compared to single data rate (SDR) SDRAM. "DDR" also refers to the first generation (DDR1), which debuted in 1998.

DDR1 operated at 2.5 V and supported transfer rates of 200, 266, 333, and 400 MT/s. Each subsequent DDR generation has increased speed, reduced voltage, and added architectural improvements while maintaining the double data rate principle.

The third generation of DDR SDRAM, introduced in 2007. DDR3 operates at 1.5 V (1.35 V for DDR3L) and supports speeds from 800 to 2133 MT/s. DDR3 DIMMs have 240 pins.

DDR3 introduced 8n prefetch (fetching 8 bits of data per clock cycle per pin), bank groups were not yet introduced. DDR3 is still widely used in legacy servers and embedded systems. Common capacities range from 1 GB to 32 GB per module.

A low-voltage variant of DDR3 that operates at 1.35 V instead of 1.5 V, reducing power consumption and heat generation. DDR3L is backward compatible with standard DDR3 systems.

DDR3L modules will operate at 1.5 V when installed in legacy DDR3 systems or when mixed with standard DDR3 modules. The lower voltage makes DDR3L particularly beneficial for laptops (longer battery life) and servers (reduced cooling requirements).

The fourth generation of DDR SDRAM, launched in 2014. DDR4 operates at 1.2 V and supports speeds from 1600 to 3200 MT/s. DDR4 DIMMs have 288 pins with a curved bottom edge for easier insertion.

DDR4 introduced bank groups (4 groups of 4 banks for x4/x8 devices), which allow faster back-to-back access to different groups. DDR4 also doubled the number of internal banks from 8 to 16 compared to DDR3. Maximum module capacity reached 256 GB with LRDIMMs using 3D stacked DRAM.

The fifth and current generation of DDR SDRAM, launched in 2020. DDR5 operates at 1.1 V and supports speeds from 3200 to 7200 MT/s (and beyond with CUDIMM). DDR5 DIMMs have 288 pins with a different key notch position than DDR4.

DDR5 introduced several major architectural changes: on-module PMIC for power management, two independent 32-bit subchannels (replacing the single 64-bit channel), doubled burst length (BL16), doubled banks (32 banks in 8 groups), on-die ECC (ODECC), and same-bank refresh. These changes significantly improve bandwidth, efficiency, and reliability.

A letter designation (e.g., B-die, C-die, D-die) assigned by DRAM manufacturers to identify a specific chip design and density. Different die revisions of the same density may have different performance characteristics and overclocking potential.

For example, Samsung B-die DDR4 chips were renowned for excellent overclocking characteristics. Die revisions represent manufacturing process improvements and design changes within the same density class.

A type of memory module with separate electrical contacts on each side of the printed circuit board (PCB), allowing independent data transfer on each side. DIMMs are the standard form factor for desktop and server memory.

DIMMs replaced SIMMs (Single In-Line Memory Modules) in the late 1990s. A standard DIMM has a 64-bit data bus (or 72-bit with ECC). DDR4 DIMMs have 288 pins, while DDR5 DIMMs have 288 pins with a different key notch position to prevent incorrect installation.

The most common type of RAM technology used in computers today. DRAM stores each bit of data in a capacitor within an integrated circuit. Because capacitors leak charge, DRAM must be periodically refreshed to retain data.

DRAM is "dynamic" because it requires constant refresh, unlike SRAM (Static RAM) which holds data as long as power is supplied. DRAM is cheaper and denser than SRAM, making it the standard for main system memory. All DDR memory modules use DRAM chips.

The storage capacity of an individual DRAM chip, measured in gigabits (Gb). Higher-density chips enable higher-capacity modules. Common densities are 4 Gb and 8 Gb for DDR3, 4 Gb to 16 Gb for DDR4, and 16 Gb to 32 Gb for DDR5.

DDR5 introduced a non-binary density of 24 Gb (between 16 Gb and 32 Gb), enabling intermediate module capacities such as 48 GB and 96 GB. Density generally doubles between DDR generations.

A JEDEC designation for a DDR5 server module with a 72-bit data width (64 data bits + 8 ECC bits per sub-channel, totaling 72 bits). EC4 provides standard single-bit error correction.

A JEDEC designation for a DDR5 server module with an 80-bit data width (64 data bits + 16 ECC bits, or 8 ECC bits per sub-channel). EC8 provides enhanced error correction capabilities beyond standard EC4.

An algorithm implemented in the memory controller that can detect and correct single-bit errors and detect multi-bit errors in memory data. ECC requires additional DRAM chips on the module to store parity/check bits.

Standard ECC uses a 72-bit data path (64 data bits + 8 ECC bits) and can correct any single-bit error and detect any two-bit error per 64-bit word. ECC is essential for servers, workstations, and any system where data integrity is critical. ECC memory requires a processor and chipset that support it.

A type of non-volatile memory chip used on memory modules to store the SPD (Serial Presence Detect) data. The EEPROM retains the module's specification data even when power is removed.

The physical size, shape, and connector type of a memory module as defined by JEDEC standards. Common DRAM form factors include DIMM (desktop/server), SODIMM (laptop), and CAMM2 (thin laptop).

BIOS-adjustable speed ratios between the processor's memory controller and the memory modules. Gear 1 runs both at the same speed (1:1) for lowest latency; Gear 2 halves the controller speed, allowing higher module speeds at a latency cost.

Gear 1 provides the best latency and is preferred for gaming and latency-sensitive workloads. Gear 2 and Gear 4 allow the system to run memory at higher data rates, which can benefit bandwidth-intensive workloads despite the increased latency. Available on Intel 11th Gen+ and AMD Ryzen platforms.

A high-performance DRAM technology that stacks multiple DRAM dies vertically using through-silicon vias (TSVs) and connects them to a processor via a silicon interposer. HBM provides much higher bandwidth and lower power per bit than standard DDR.

Developed by AMD and adopted by JEDEC in 2013. HBM uses a very wide interface (1024 bits per stack) at relatively low clock speeds to achieve high bandwidth. It has evolved through HBM, HBM2, HBM2E, HBM3, and HBM3E generations. HBM3E offers up to 1.2 TB/s bandwidth per stack. Major producers are SK Hynix, Samsung, and Micron.

The third generation of High Bandwidth Memory. HBM3 supports up to 819 GB/s per stack, while HBM3E extends this to approximately 1.2 TB/s. Used in AI accelerators (NVIDIA H100/H200, AMD MI300) and HPC systems.

HBM3E stacks up to 12 DRAM dies with capacities up to 36 GB per stack. It operates at up to 9.6 Gb/s per pin. The technology is critical for AI training and inference workloads that require massive memory bandwidth.

The upcoming fourth generation of High Bandwidth Memory, expected to enter mass production in 2025-2026. HBM4 will double the interface width to 2048 bits per stack and is projected to exceed 1.5 TB/s bandwidth.

SK Hynix announced the world's first HBM4 development completion in September 2025. HBM4 is designed for next-generation AI processors including NVIDIA Rubin. It will support higher capacities through increased die stacking and wider interfaces.

A metal shield attached to a memory module to dissipate heat from the DRAM chips. Common on high-performance and overclocked modules, heat spreaders improve thermal management and module longevity.

The global standards organization for the microelectronics industry. JEDEC defines the specifications for DDR memory (DDR3, DDR4, DDR5, HBM), including electrical characteristics, timings, pin assignments, and form factors.

JEDEC is a consortium of over 300 member companies including Samsung, Micron, SK Hynix, Intel, and AMD. All standard DDR memory modules conform to JEDEC specifications. Speeds and timings beyond JEDEC specifications are considered overclocking (XMP/EXPO).

A low-power variant of DDR5 designed for mobile devices, thin laptops, and automotive applications. LPDDR5 supports speeds up to 6400 Mbps, while LPDDR5X extends this to 8533 Mbps with improved power efficiency.

LPDDR5/5X uses a different package and interface than standard DDR5 DIMMs. It is soldered directly to the motherboard in most implementations. LPDDR5X offers approximately 20% better power efficiency than LPDDR5 at equivalent speeds. Major suppliers include Samsung, SK Hynix, and Micron.

A server memory module that features data buffers in addition to a register, reducing the electrical load on the memory controller. This enables higher capacity configurations without reducing memory speed.

LRDIMMs use data buffers to isolate the DRAM chips from the memory bus, reducing the electrical load that the memory controller must drive. This allows for higher-density modules (e.g., quad-rank or octal-rank) to operate at full speed, whereas equivalent RDIMM configurations might require speed reductions. LRDIMMs are used in servers requiring maximum memory capacity.

The data transfer path between a memory module and the memory controller (typically integrated in the CPU). Modern systems use multi-channel architectures where identical modules installed across channels aggregate bandwidth.

Dual-channel doubles effective bandwidth, quad-channel quadruples it. Server processors (Intel Xeon, AMD EPYC) support up to 8 or 12 memory channels. For optimal performance, identical modules should be installed in matching channel slots as specified by the motherboard manual.

A set of parameters that define the latency of various DRAM operations, typically expressed as four numbers: CL-tRCD-tRP-tRAS (e.g., 16-18-18-36 for DDR4, or 40-39-39-76 for DDR5). Lower numbers indicate faster response times.

Beyond the four primary timings, there are dozens of secondary and tertiary timings (tRFC, tFAW, tWR, tRRD, etc.) that can be tuned for performance. JEDEC defines default timings for each speed grade, while XMP/EXPO profiles may specify tighter (lower) timings for overclocking.

A JEDEC-standard DDR5 server module that uses multiplexed data buffers and a special register (MRCD) to operate two ranks simultaneously, effectively doubling transfer rates. First-generation MRDIMMs start at 8800 MT/s.

MRDIMMs deliver 128 bytes of data to the processor at once by operating two ranks in parallel through multiplexing. This provides significantly higher bandwidth than conventional RDIMMs. Second-generation MRDIMMs target 12,800 MT/s.

A memory module that does not include the additional DRAM chips required for Error Correction Code. Non-ECC modules have a 64-bit data path (x64) and are standard in consumer desktops and laptops.

Error correction built into the individual DDR5 DRAM chip itself, capable of correcting single-bit errors within the chip before data is sent to the module's data bus. Introduced with DDR5 as a mandatory feature.

On-die ECC operates transparently and is separate from the system-level ECC performed by the memory controller. It corrects internal bit errors caused by manufacturing variations and cell degradation, improving the overall reliability of DDR5 memory. On-die ECC is present on all DDR5 chips, including those on non-ECC modules.

The multi-layered board on which DRAM chips, the register (for RDIMMs), SPD, and other components are mounted. PCB quality affects signal integrity and thus the maximum achievable speed and stability.

A formal document issued by manufacturers to announce changes to a product, including new releases, component changes, end-of-life notices, or discontinuations. PCNs are critical for supply chain management in the memory industry.

A voltage regulator chip located on every DDR5 memory module that manages power distribution to the DRAM chips. DDR5 moved power management from the motherboard to the module itself for more precise and efficient power delivery.

In DDR4 and earlier, the motherboard's voltage regulator supplied power to the memory modules. DDR5's on-module PMIC converts the 5V input to the precise 1.1V required by the DRAM chips, reducing noise and improving power efficiency. The PMIC also enables per-module voltage control.

A list published by motherboard and system manufacturers showing which specific memory modules have been tested and verified to work with their products. Checking the QVL is recommended when selecting memory for a new build.

A 64-bit-wide block of DRAM chips on a module that can be accessed independently. A single-rank (1R) module has one set of chips forming a 64-bit data path; a dual-rank (2R) module has two such sets, but only one rank can be accessed at a time.

The number of ranks is determined by the DRAM width and module capacity. For example, a 16 GB module using x8 chips needs 8 chips for one rank (8 chips × 8 bits = 64 bits). Common configurations are 1R (single), 2R (dual), 4R (quad), and 8R (octal). More ranks per module increase capacity but may reduce maximum speed due to electrical loading.

A set of chipset and platform features that provide enhanced memory redundancy for mission-critical systems. RAS features include ECC, memory mirroring, memory sparing, lockstep mode, and patrol scrubbing.

Memory mirroring duplicates data across two channels for redundancy. Memory sparing reserves a rank as a hot spare. Lockstep combines two channels for wider ECC coverage. Patrol scrubbing periodically reads and corrects all memory in the background. These features are found in server and workstation platforms.

A server-class memory module that includes a register component, also known as a Registered Clock Driver (RCD), which acts as a buffer between the DRAM chips and the memory controller. This allows higher capacities and more modules per channel than UDIMMs.

The register buffers the command and address signals, using one additional clock cycle to synchronize data. This extra cycle adds a small amount of latency but enables the memory controller to support more DRAM chips per module and more modules per channel. Most server and workstation chipsets require RDIMMs. RDIMMs are available in x4 and x8 DRAM configurations.

The periodic process of reading and rewriting data in DRAM cells to prevent data loss. DRAM stores data as electrical charges in capacitors, which leak over time and must be refreshed typically every 32 or 64 milliseconds.

DDR5 introduced same-bank refresh, allowing one bank to be refreshed while other banks remain accessible. Previous DDR generations required all-bank refresh, which temporarily blocked all memory access. This improvement significantly reduces the performance impact of refresh operations in DDR5.

A buffer component on RDIMMs that sits between the DRAM chips and the memory controller. It re-drives the command, address, and clock signals, improving signal integrity and enabling support for more DRAM chips per module.

The register adds one clock cycle of latency but allows the memory controller to support higher capacities and more modules per channel. DDR5 RDIMMs use an RCD (Registered Clock Driver) that also manages the two sub-channels independently.

An advanced ECC feature available with x4 DRAM configurations that can correct all errors from a single failed DRAM chip. Also known as Chipkill (IBM) or ADDDC (Intel). Requires x4 RDIMMs or LRDIMMs.

Because x4 chips contribute only 4 bits to the 72-bit ECC word, the ECC algorithm has enough redundancy to correct all 4 bits if one chip fails completely. This is critical for server reliability, as it allows the system to continue operating even with a failed DRAM chip.

A type of DRAM that synchronizes its operations with the system clock, enabling the memory controller to predict when data will be ready. All modern DDR memory is synchronous DRAM.

Before SDRAM, asynchronous DRAM required the controller to wait for data without knowing exactly when it would arrive. SDRAM synchronizes data transfers with the rising edge of the clock. DDR SDRAM further improved this by transferring data on both clock edges.

A compact memory module form factor designed for laptops, small form factor PCs, and embedded systems. SODIMMs are roughly half the physical size of standard DIMMs.

DDR4 SODIMMs have 260 pins, while DDR5 SODIMMs have 262 pins. SODIMMs are available in non-ECC and ECC variants. They use the same DRAM technology as full-size DIMMs but in a smaller physical package. Beginning with DDR5 at 6400 MT/s, JEDEC requires a Client Clock Driver (CKD) on SODIMMs, creating the CSODIMM variant.

A small EEPROM chip on every memory module that stores the module's specifications: capacity, speed, timings, voltage, manufacturer, and part number. The system BIOS reads the SPD at boot to configure the memory controller correctly.

DDR5 upgraded from a simple EEPROM to an SPD Hub (SPD5 Hub) with an I3C interface, enabling faster reads and additional features like temperature monitoring. XMP and EXPO overclocking profiles are also stored in the SPD.

A DDR5 architectural feature that divides the module's 64-bit data bus into two independent 32-bit segments. Each sub-channel can be addressed and operated independently, improving efficiency and reducing access granularity.

In DDR4, the entire 64-bit bus is accessed as one unit (minimum 64 bytes per access). DDR5's two 32-bit sub-channels allow two independent 32-byte accesses simultaneously, which better matches modern CPU cache line access patterns and improves effective bandwidth utilization.

The minimum number of clock cycles that a row must remain open (active) before it can be precharged (closed). It is the fourth number in the standard timing notation and is typically the largest of the four primary timings.

The minimum number of clock cycles between activating a row (opening it) and issuing a read or write command to a column within that row. It is the second number in the standard timing notation (e.g., CL-tRCD-tRP-tRAS).

The minimum number of clock cycles required to close (precharge) an active row before a new row in the same bank can be opened. It is the third number in the standard timing notation.

A vertical electrical connection that passes completely through a silicon die, enabling 3D stacking of multiple DRAM dies in technologies like HBM. TSVs provide thousands of parallel connections between stacked dies.

A memory module without a register or buffer between the DRAM chips and the memory controller. UDIMMs communicate directly with the CPU memory controller, offering lower latency but supporting fewer modules per channel.

UDIMMs are the standard choice for desktops, workstations, and consumer PCs. They are available in non-ECC (64-bit, x64) and ECC (72-bit, x72) variants. Because there is no buffer, the memory controller must drive all DRAM chips directly, which limits the number of ranks and modules that can be supported per channel.

A JEDEC classification for memory modules with reduced physical height, designed for thin-profile server and embedded systems. VLP UDIMMs and RDIMMs for DDR3/DDR4 have a height of 18.75 mm, compared to 31.25 mm for standard DDR4/DDR5 DIMMs.

The operating voltage of a memory module, which has decreased with each DDR generation to reduce power consumption and heat. DDR3 operates at 1.5 V (1.35 V for DDR3L), DDR4 at 1.2 V, and DDR5 at 1.1 V.

Lower voltage reduces power consumption quadratically (power is proportional to voltage squared), which is significant in data centers with thousands of modules. Overclocked modules may operate at slightly higher voltages (e.g., 1.25-1.35 V for DDR5 XMP profiles).

An Intel specification that allows memory manufacturers to store pre-tested overclocking profiles in the module's SPD. Enabling XMP in the BIOS applies higher-than-JEDEC speeds and tighter timings with a single setting.

XMP 2.0 supports DDR4 with up to two profiles. XMP 3.0 supports DDR5 with up to five profiles (three vendor-defined, two user-customizable). XMP profiles specify speed, voltage, and all primary/secondary timings. Modules with XMP are tested by the manufacturer to be stable at the advertised speeds.